

When provided in software, MEJ32 is a 32/64-bit virtual core optimized for various embedded systems processors including ARM Cortex-M, ARM Cortex-A, Renesas RX and V850, MIPS32, Infineon TriCore, and Tensilica Xtensa. When provided in hardware, it is a regular core IP, qualified as a VPU.
MEJ32 provides a unique instruction set architecture (ISA). The MicroEJ SOAR Linker combines Java bytecode (.class) and WebAssembly (.wasm) files, transforming them into MEJ32-executable code and linking them into a single ELF binary. This enables applications written in multiple languages to run within the same runtime environment.
For hardware version of the MEJ32 core, please contact MicroEJ for availability.
MicroEJ offers MICROEJ MEJ32 implementations for a wide range of popular hardware architectures. Examples of MICROEJ VEE are available for dedicated evaluation boards.
Follow the link below in order to find out if your hardware is supported and which MICROEJ VEE implementation is right for your project according to your processor core architecture and C tool chain.