MEJ32 is a 32-bit virtual core optimized for various embedded systems processors including ARM Cortex-M, ARM Cortex-A, Renesas RX and V850, MIPS32, Infineon TriCore, and Tensilica Xtensa.
MEJ32 provides a unique Instruction Set Architecture (ISA). A tool, named SOAR, generates MEJ32 ISA code in ELF format, out of the binary J2VM ISA code format. The SOAR also acts as a linker.
For hardware version of the MEJ32 core, please contact MicroEJ for availability.
MicroEJ offers MICROEJ MEJ32 implementations for a wide range of popular hardware architectures. Examples of MICROEJ VEE are available for dedicated evaluation boards.
Follow the link below in order to find out if your hardware is supported and which MICROEJ VEE implementation is right for your project according to your processor core architecture and C tool chain.